Test & Debug

(Include Test)

Roa Logic provides Silicon-Proven IP solutions for FPGA and ASIC implementations. All IP comes packed with a full featured testbench and documentation. In addition custom solutions are provided on request.

The majority of our IPs are available for direct download for free, from our GitHub repositories for non-commercial applications. For commercial applications or if you find any IP missing or would like modifications please contact us.

Contact

(Parameter Test)

Roa Logic BV
Burgemeester Snijdersstraat 17
6363BG Wijnandsrade
The Netherlands

☎︎ +31 (45) 405 5681
✉︎ info@roalogic.com
➤ https://roalogic.com

IBAN: NL75 INGB 0006 5617 87, BIC: INGBNL2A

KvK Zuid-Limburg: 61368962
BTW: NL854314283B01

Meta-Test

(GH Metadata Test)

Owner: RoaLogic

Public Repos:

• 8b10b

• adv_dbg_if

• adv_jtag_bridge

• ahb3lite_apb_bridge

• ahb3lite_error

• ahb3lite_interconnect

• ahb3lite_memory

• ahb3lite_pkg

• ahb3lite_sdram_ctrl

• ahb3lite_timer

• apb4_gpio

• apb4_mux

• apb4_uart16550

• apb_error

• Hamming-ECC

• memory

• OpenOCD

• plic

• riscv-isa-manual

• riscv_gnu_eclipse

• rltheme

• roalogic.github.io

• RV12

• rv_c_demos

• rv_soc

• universal_jtag_tap

• Verilator-simulation

• vga_lcd

• vi_systemverilog_syntax

main

---

Markdown

(Markdown Styling Demo)

Heading 1

Heading 2

Heading 3

Heading 4

Heading 5

Heading 6

Blockquote

Some inline code

Code Block

Column 1	Column 2	Column 3
Text	Text	Text

1. List 1
2. List 2
3. List 3

• Bullet 1
  • Bullet 2
    • Bullet 3