Welcome!

Roa Logic provides Silicon-Proven IP solutions for FPGA and ASIC implementations. All IP comes packed with a full featured testbench and documentation. In addition custom solutions are provided on request.

The majority of our IPs are available for direct download for free, from our GitHub repositories for non-commercial applications. For commercial applications or if you find any IP missing or would like modifications please contact us (info@roalogic.com).

Projects

The following projects are current available as GitHub repositories:

• RV12 RISC-V CPU Core
• RISC-V PLIC Core
• AHB-Lite Timer
• AHB-Lite Memory
• AHB-Lite Multi-Layer Switch
• AHB-Lite / APB4 Bridge
• APB4 Multiplexer
• APB4 GPIO

Non-Commercial & BSD License Terms

Roa Logic provides most of it’s cores for free for non-commercial applications and purposes.”Non-Commercial” or “BSD” style license agreements apply and are included in each IP repository.

About Us

Overview

Founded in 2014 by Richard Herveille, Roa Logic BV specialises in the development of Intellectual Property Cores for FPGA and ASIC, with a strong focus on the embedded market. We provide the IP required to build a complete embedded solution, including processors, peripherals, memory, and interfaces.

Roa Logic offers its IP for download from its GitHub page. All IP can be tested and used for non-commercial applications for free. For support, modifications, and commercial usage a fee charged. This business model allows our customers to test our IP and develop and test their application before making any financial commitments.

Competency

Roa Logic expertise covers System, Hardware and Software development of FPGA and ASIC applications including:

• 15+ Years of experience in FPGA and ASIC development, including Architecture specifications, RTL design, Verification, Synthesis, prototyping, test, debug.
• 10+ Years of experience in programmable logic architecture design, including architecture specifications, software requirements, process & design flow specifications and implementation.

Design Methodology

Roa Logic leverages technology independent HDL (Hardware Description Language) using a strict and robust top down design methodology. All IP is simulated at behavioral and gate levels and are provided with methodology scripts, exhaustive standard compliance verification suites and complete documentation.

Products

Roa Logic’s portfolio consists of RISC-V compliant embedded processors featuring AMBA Interfaces, associated peripherals & interfaces, bridging & switching and error correction cores

Contact

Roa Logic BV
Burgemeester Snijdersstraat 17
6363BG Wijnandsrade
The Netherlands

☎︎ +31 (45) 405 5681
✉︎ info@roalogic.com
➤ https://roalogic.com

IBAN: NL75 INGB 0006 5617 87, BIC: INGBNL2A

KvK Zuid-Limburg: 61368962
BTW: NL854314283B01